WHAT IS RC TERMINATION IN PCB DESIGN ?

In this tutorial we are going to lean about WHAT IS RC TERMINATION IN PCB DESIGN ?

AC termination is recommended most for clock applications. An example of AC
termination is when a 75? impedance is coupled with a 100pF capacitor. That allow for leakage in input impedance of the receiver, A resistor is selected to be larger than the trace impedance. That allow for rapid transition of the clock edge, the capacitor value is selected at 120pF. The higher capacitor value allows for heavier current levels to pass. However, higher capacitive values increases power dissipation.
Capacitor values less than 50pF diminish the effectiveness of termination.
This method terminates the signal transition & therefore should be calculated based on the edge rate. This method’s disadvantage is that 2 components are needed for each line. Termination packs are sometimes used to reduce component count. Be aware that signal coupling can occur between signals in the termination pack. An RC circuit arranged in series to a voltage source, usually ground, makes a dynamic termination. The result of this is the cut off of glitches & overshoot.

What is Termination in PCB Layout Design ?

In this tutorial we are going to learn about What is Termination in PCB Layout Design ?

A component (typically a resistor/diode) added at the end of the line to establish a relationship of the load/source impedance with line impedance. The termination of interconnect topological is required when increasing clock frequencies & faster rise & fall times begin to impact the electrical performance parameters on the PCB. For high speed board design, there are 5 common termination techniques described below which may be a lied to the design to contain the impact on signal integrity & losses.
Some commonly known termination techniques are series termination,parallel termination & Thevenin termination.

WHAT IS PROCESS OF PCB DESIGN ?

In this tutorial we are going to learn about WHAT IS PROCESS OF PCB DESIGN ?

1) BILL OF MATERIAL ( BOM)

Tabulation of all parts and materials used in the construction of a printed board
assembly Can be a Separate Parts List or Integral Parts List
Minimum information required per IPC-D-325:
Item (Find) Number
Electrical component cross-reference
part Information
(1) Components (2) Hardware (3) Bulk Materials
Quantities
Referenced Processes

SCHEMATIC For PCB


· In Schamatic , Electrical connection of all components as per provided by hardware team .
In Schematic All Reference of components should be proper
In scematic must be check DRC before create Net list
GND & Power track should be proper separate by Symbol
VCC decoupling Capacitor place near to IC pin of VCC.
Crystal placement close to controller .

PCB Design Layout


first Check the all connection with schematic
Second placement of all components step by step as per flow of schematic
In PCB design Analog & Digital track should be separate as per schematic
GND layer design at bottom layer so that it would be work as a heat shink
High Power track should be from low power signal

GERBER For PCB

After final the PCB design the set the Gerber setting as per Layer.
Like if Gerber is one then we set the Bottom, SSB, SST, Solder masking & drill Layer

What is PCB Design & Manufacturing ?

In this tutorial we are going to learn about What is PCB Design & Manufacturing ?

Manufacturing For PCB
• First to utilize advancement in automation and computers
• Digitizing replaces photo-reduction
• NC Drill replaced “Bulls eye” drilling
• Photographic imaging to create silk screens
• “Pick & Place” machines for component mounting
• Wave solder machines reduces hand soldering
Designing For PCB
• Hand drawing layouts(2x,4x) digitized to create 1x film artwork
• CAD programs developed for board layout
• Output of Gerber data to create 1x film artwork
• Output of NC Drill tapes

What are the PCB thicknesses of FR-4 Laminates?

In this tutorial we are going to learn about What are the PCB thicknesses of FR-4 Laminates?

FR4 Double sided (Rigid laminate)
thickness copper (h=half ounce = 17μ, 1 = 1 ounce = 35μ, 2 = 1 ounce = 70μ)
0,80mm h-h
1,55mm h-h
1,55mm 1-1
1,55mm 2-2
2,00mm 1-1
2,00mm h-h
2,40mm h-h
2,40mm 1-1
3,20mm 1-1
FR4 Multilayer (Thin laminate)
0,002 h-h
0,005 h-1
0,005 1-1
0,008 1-1
0,008 1-2
0,008 2-2
0,010 1-1
0,014 h-1
0,014 1-1
0,014 2-1
0,014 2-2
0,018 h-1
0,018 1-1
0,022 h-1
0,022 1-1
0,022 1-2
0,022 2-2
0,028 1-1
0,028 2-2

0,028 h-1
0,036 1-1
Polyimide laminate
0,005 h-1
0,005 1-1
0,008 2-1
0,008 2-2
0,008 1-1
0,010 1-2
0,010 2-2
0,022 1-2
0,022 2-2
Flexible laminates
Rogers product series 2000:
20FR-C-110 2 mils polyimide, 1 mil acrylic adhesive
20FR-C-210 2 mils polyimide, 2 mil acrylic adhesive
Dupont AP series:
AP8525 2 mils adhesiveless 17/17 copper
AP9121 2 mils adhesiveless 35/35 copper
AP9222 2 mils adhesiveless 70/70

What is Guide lines for Ground Planes in PCB design

In this tutorial we are going to learn about What is Guide lines for Ground Planes in PCB design

Inadequate return path(grounding is one of the major sources of emission. If its not correctly designed.
Try to keep it as short as possible. To improve the return path(through the ground), suggestions are,
· Have a solid ground plane in the PCB stack-up. This ensures that a ground return path is always
running underneath the high frequency and power traces.
· Stitch all the ground planes together to ensure equal potential
· Fill all unused open areas between traces on signal layers with the GND & stitch it to the adjacent ground plane.
· In PCB design the ground plane should be as large as possible.
· Border the PCb with chassis GND or place the VCC plane back from the edge of the board by 3
times the distance between the planes.
· Use multi point grounding to keep GND impedance low at high frequency.
· Keep the ground plane uninterrupted(avoid traces & via on ground planes).

WHAT IS BGA IN PCB DESIGN ?

In this tutorial we are going to learn about WHAT IS BGA IN PCB DESIGN ?

Pitch varies from 1.5mm to 1.0 mm


BGA Advantages

  1. BGAs are usually smaller.
  2. BGAs have larger pitch.
  3. BGAs have no TH leads, that causes yield and rework problems.
  4. Board assembly yields are significantly improved.
  5. Board inspection can be reduced.
  6. BGAs have better thermal and electrical properties.
  7. In many Project, the use of BGA results in significant system level cost savings.
  8. Self alignment during soldering process
  9. Low assembly cost
  10. Repairable
  11. Reduced component cost
  12. Fewer production reject
  13. Smaller area board and yet, larger I/O pitch
  14. Assembled with same SMT equipment as QFP
  15. In general, BGAs have better electrical properties than their QFP counterparts
  16. BGAs are less fragile and easier to handle both before & during assembly
  17. The placement operation is usually far easier & more reliable than for fine-pitch QFP’s
  18. A much higher assembly yield is generally expected using BGAs
  19. The smaller package size/the higher I/O count allows a further step in miniaturization
    BGA Disadvantages
  • There are problems & costs associated with PCB routing, especially for full matrix package
  • BGAs are more sensitive to moisture uptake & more prone to give pop corning effects
  • Verify of the solder joints is impossible without costly x-ray equipment
  • BGA packages may be have coplanarity problems, particularly for larger devices
  • Reliability not yet proven due to many design & assembly parameters still being changed
  • Board level rework potentially more difficult

What is Differential Clocking in PCB design ?

In this tutorial we are going to learn about What is Differential Clocking in PCB design ?

PCB  designer would route the 2 traces together in parallel. A clock bar has equal & opposite current with the primary clock and is also 180° out of phase.

The EMI generated  due to differential clocking is caused by H-field cancellation. Since H-fields travel with current flow according to the right-hand rule, two currents flowing in opposite directions and 180° out of phase will have their H-fields cancelled. Reducing H-fields results in lower emissions.

Differential clocking may be  reduce the amount of noise coupled to I/O traces, which are EMI generating paths because they leave the system. A single-ended clock’s return path is usually a reference plane, which is shared by other signals or traces. If noise is created on a single-ended clock, the noise will appear on the reference plane and may be coupled to I/O traces. A differential clock’s return path is the clock bar signal and trace, which is more isolated than the reference plane and reduces I/O trace coupling. For best results,

• The trace lengths & the 180° phase difference between the 2 clocks needs to be closely matched.

• The real & parasitic terminations of each differential pair line should be the same.

The spacing between the 2 traces should be as small as possible. Placing GND traces on the outside ofhe differential pair may further reduce emissions. Intermediate vias to GND may be needed to reduce the opportunity for re-radiation from the GND traces themselves. Distance between vias is related to the clk trace’s frequency. Since this is specific to the type of clk, see specific design guidelines for it Implementation.

What is high speed PCB Design ?

In this tutorial we are going to learn about What is high speed PCB Design ?

A circuit is considered high-speed “when the rise/fall time of a signal is fast enough that the signal may be change from one logic state to the other in less time than it takes for it to travel the length of the conductor and back. Generally one From this definition it is obvious that two critical factors determine if a circuit is operating at a high-speed: the switching time of the device(s) on the circuit & the length of the circuit. It is important to note that the “clock speed” of the circuit does not determine whether it is operating in the high-speed domain.

  • Use 45° angle or smooth curves, in order to minimize signal reflection. Sharp corners have a high field strength.
  • Avoid stubs or tees, vias, sharp 90° turns, all of which cause impedance discontinuities.
  • Minimize the number of signals that cross PWR domains. Each PWR plane should have HF decoupling caps between the planes to provide a return path for signals that cross from one domain to another.
  • Consider using buried capacitance pwr or gnd planes. This technology reduces HF bypass capacitor count. Unfortunately, this technology is expensive & of limited availability. The added cost can be partially offset by savings in HF capacitors.
  • Use all available pwr & gnd pins. This may seem obvious but it is not always done. Some schematic symbols define VCC & GND connections implicitly so they are not visible on the schematic. Therefore, it may not be apparent that some are missing. It is preferred to specify pwr & gnd explicitly on the schematic.
  • Consider board stackup order. It is preferable to have the gnd plane as close as possible to the components. Place the VCC plane towards the bottom side of the board.
  • Border the PCB with chassis gnd or place the VCC plane back from the edge of the board by three times the distance between planes.
  • Microstrip should only be used for short traces, traces with slow rise time signals & where driver & load are isolated from clock. (In practice, Microstrip is used for all signals &clks)
  • Stripline should be used when possible. It is especially desirable for clocks. (In practice it is rarely used on 4-layer boards.)
  • Keep clock chips or clock lines away from the edges of the board.
  • Minimize the trace length of clock lines.
  • Keep clocks away from I/O lines and connectors.
  • Avoid running traces under crystals, clock chips, or other “hot” circuits. (Hot in the EMI sense means noisy, HF/high energy, not high temp.) A good way to ensure this is to put a cross-hatched gnd plane on the surface under the oscillator/clock chip, which prevents crosstalk between the clock & signals.
  • To minimize crosstalk, use a trace spacing-to-height ratio greater than 2. Unfortunately, this is seldom practical due to space constraints. Usually, the designer must settle for approximately 1:1. Good signal integrity tools are important in this context.
  • Put line driver & receiver near the port they drive. Put filters as close to the connector as possible to prevent unwanted signals coupling into the output of the filter.
  • Use ferrites or LP filters on signals that go to an external cable.
  • Route diffl pairs together, so their lengths are matched & any common-mode noise is cancelled out.

Write some general guidelines for component placement?

In this tutorial we are going to about Write some general guidelines for component placement?

Component placement can also reason of EMI generated. The guidelines below are general Approaches to minimize EMI.

• Keep leads on TH components short. Through hole the components should be as close to the PCB as possible and trim leads if necessary.

• Place all components associated with one clock trace closely together. This reduces the trace length & Reduces radiation.

• Placement high-current devices should be  as closely as possible to the power sources.

• Minimize the use of sockets in HF portions of the board. Sockets introduce higher inductance & mis-Matched impedance.

• Keep crystal, oscillators, & clk generators away from I/O ports & board edges. EMI from these devices can be coupled onto the I/O ports.

• Placement of crystals so that they lie flat against the PC board. This minimizes the distance to the GND Plane & provides better coupling of EM fields to the board.

• Connect the crystal retaining straps to the GND plane. These straps, if ungrounded, can behave as an antenna and radiate.

• Provide a GND pad equal/larger than footprint under crystals & oscrs on the component side of the board. This GND pad should be tied to the GND planes with multiple vias.