In this tutorial we will learn about Serial Communication Comparison
In this tutorial we are going to learn about PCB SPECIFICATION SHEET
|PCB SCIENTIST Pvt. Ltd.||PCB SPECIFICATION SHEET||DOC. No. : FM/RD/11|
REV No. : 02
DATE : 01-07-2010
|1||PCB Drawing No.||LD-22P0-S001-R00|
|2||PCB Type||Single Sided|
|3||PCB unit Size||22×30 MM|
(Outer & Inner layers)
|35 µM Finish|
|8||Panel Lay-up(X * Y)||5×4|
|9||PCB unit per Panel||20|
|10||PCB Panel size||120×130 MM|
|11||Panel Fudicial Mark||Global|
|13||Solder Mask||white, top side only|
|14||Legend Printing||Black, single side|
|Note 1:||Given drill size should be maintain as per drawing.|
|Date||Prepared by||Approved by|
In this tutorial we are going to lean about WHAT IS RC TERMINATION IN PCB DESIGN ?
AC termination is recommended most for clock applications. An example of AC
termination is when a 75? impedance is coupled with a 100pF capacitor. That allow for leakage in input impedance of the receiver, A resistor is selected to be larger than the trace impedance. That allow for rapid transition of the clock edge, the capacitor value is selected at 120pF. The higher capacitor value allows for heavier current levels to pass. However, higher capacitive values increases power dissipation.
Capacitor values less than 50pF diminish the effectiveness of termination.
This method terminates the signal transition & therefore should be calculated based on the edge rate. This method’s disadvantage is that 2 components are needed for each line. Termination packs are sometimes used to reduce component count. Be aware that signal coupling can occur between signals in the termination pack. An RC circuit arranged in series to a voltage source, usually ground, makes a dynamic termination. The result of this is the cut off of glitches & overshoot.
In this tutorial we are going to learn about What is Termination in PCB Layout Design ?
A component (typically a resistor/diode) added at the end of the line to establish a relationship of the load/source impedance with line impedance. The termination of interconnect topological is required when increasing clock frequencies & faster rise & fall times begin to impact the electrical performance parameters on the PCB. For high speed board design, there are 5 common termination techniques described below which may be a lied to the design to contain the impact on signal integrity & losses.
Some commonly known termination techniques are series termination,parallel termination & Thevenin termination.
In this tutorial we are going to learn about WHAT IS PROCESS OF PCB DESIGN ?
1) BILL OF MATERIAL ( BOM)
Tabulation of all parts and materials used in the construction of a printed board
assembly Can be a Separate Parts List or Integral Parts List
Minimum information required per IPC-D-325:
Item (Find) Number
Electrical component cross-reference
(1) Components (2) Hardware (3) Bulk Materials
SCHEMATIC For PCB
· In Schamatic , Electrical connection of all components as per provided by hardware team .
In Schematic All Reference of components should be proper
In scematic must be check DRC before create Net list
GND & Power track should be proper separate by Symbol
VCC decoupling Capacitor place near to IC pin of VCC.
Crystal placement close to controller .
PCB Design Layout
first Check the all connection with schematic
Second placement of all components step by step as per flow of schematic
In PCB design Analog & Digital track should be separate as per schematic
GND layer design at bottom layer so that it would be work as a heat shink
High Power track should be from low power signal
GERBER For PCB
After final the PCB design the set the Gerber setting as per Layer.
Like if Gerber is one then we set the Bottom, SSB, SST, Solder masking & drill Layer
In this tutorial we are going to learn about What is PCB Design & Manufacturing ?
Manufacturing For PCB
First to utilize advancement in automation and computers
Digitizing replaces photo-reduction
NC Drill replaced “Bulls eye” drilling
Photographic imaging to create silk screens
“Pick & Place” machines for component mounting
Wave solder machines reduces hand soldering
Designing For PCB
Hand drawing layouts(2x,4x) digitized to create 1x film artwork
CAD programs developed for board layout
Output of Gerber data to create 1x film artwork
Output of NC Drill tapes
In this tutorial we are going to learn about What are the PCB thicknesses of FR-4 Laminates?
FR4 Double sided (Rigid laminate)
thickness copper (h=half ounce = 17μ, 1 = 1 ounce = 35μ, 2 = 1 ounce = 70μ)
FR4 Multilayer (Thin laminate)
Rogers product series 2000:
20FR-C-110 2 mils polyimide, 1 mil acrylic adhesive
20FR-C-210 2 mils polyimide, 2 mil acrylic adhesive
Dupont AP series:
AP8525 2 mils adhesiveless 17/17 copper
AP9121 2 mils adhesiveless 35/35 copper
AP9222 2 mils adhesiveless 70/70
In this tutorial we are going to learn about What is Guide lines for Ground Planes in PCB design
Inadequate return path(grounding is one of the major sources of emission. If its not correctly designed.
Try to keep it as short as possible. To improve the return path(through the ground), suggestions are,
· Have a solid ground plane in the PCB stack-up. This ensures that a ground return path is always
running underneath the high frequency and power traces.
· Stitch all the ground planes together to ensure equal potential
· Fill all unused open areas between traces on signal layers with the GND & stitch it to the adjacent ground plane.
· In PCB design the ground plane should be as large as possible.
· Border the PCb with chassis GND or place the VCC plane back from the edge of the board by 3
times the distance between the planes.
· Use multi point grounding to keep GND impedance low at high frequency.
· Keep the ground plane uninterrupted(avoid traces & via on ground planes).
In this tutorial we are going to learn about WHAT IS BGA IN PCB DESIGN ?
Pitch varies from 1.5mm to 1.0 mm
- BGAs are usually smaller.
- BGAs have larger pitch.
- BGAs have no TH leads, that causes yield and rework problems.
- Board assembly yields are significantly improved.
- Board inspection can be reduced.
- BGAs have better thermal and electrical properties.
- In many Project, the use of BGA results in significant system level cost savings.
- Self alignment during soldering process
- Low assembly cost
- Reduced component cost
- Fewer production reject
- Smaller area board and yet, larger I/O pitch
- Assembled with same SMT equipment as QFP
- In general, BGAs have better electrical properties than their QFP counterparts
- BGAs are less fragile and easier to handle both before & during assembly
- The placement operation is usually far easier & more reliable than for fine-pitch QFP’s
- A much higher assembly yield is generally expected using BGAs
- The smaller package size/the higher I/O count allows a further step in miniaturization
- There are problems & costs associated with PCB routing, especially for full matrix package
- BGAs are more sensitive to moisture uptake & more prone to give pop corning effects
- Verify of the solder joints is impossible without costly x-ray equipment
- BGA packages may be have coplanarity problems, particularly for larger devices
- Reliability not yet proven due to many design & assembly parameters still being changed
- Board level rework potentially more difficult
In this tutorial we are going to learn about What is Differential Clocking in PCB design ?
PCB designer would route the 2 traces together in parallel. A clock bar has equal & opposite current with the primary clock and is also 180° out of phase.
The EMI generated due to differential clocking is caused by H-field cancellation. Since H-fields travel with current flow according to the right-hand rule, two currents flowing in opposite directions and 180° out of phase will have their H-fields cancelled. Reducing H-fields results in lower emissions.
Differential clocking may be reduce the amount of noise coupled to I/O traces, which are EMI generating paths because they leave the system. A single-ended clock’s return path is usually a reference plane, which is shared by other signals or traces. If noise is created on a single-ended clock, the noise will appear on the reference plane and may be coupled to I/O traces. A differential clock’s return path is the clock bar signal and trace, which is more isolated than the reference plane and reduces I/O trace coupling. For best results,
• The trace lengths & the 180° phase difference between the 2 clocks needs to be closely matched.
• The real & parasitic terminations of each differential pair line should be the same.
The spacing between the 2 traces should be as small as possible. Placing GND traces on the outside ofhe differential pair may further reduce emissions. Intermediate vias to GND may be needed to reduce the opportunity for re-radiation from the GND traces themselves. Distance between vias is related to the clk trace’s frequency. Since this is specific to the type of clk, see specific design guidelines for it Implementation.