WHAT IS EMI & EMC IN PCB DESIGN

In this tutorial we are going to learn about WHAT IS EMI & EMC IN PCB DESIGN

EMI: It is the process which gives out disruptive EM waves, transmits energy from one electronic device to another via radiated/conducted paths. In common usage, the term refers to RF signals. EMI Generally which have the frequency range commonly identified as “anything greater than DC to daylight.”
EMC: The capability of electrical/electronic systems/equipment & devices to operate in their intended
EM environment within a defined margin of safety & at design levels/performance, without suffering or causing unacceptable degradation as a result of EMI. Any source of changing voltage anywhere in the circuit will generate emissions. The greater the voltage or current amplitude within the circuit, the greater the source of emissions. The faster that a voltage changes level, the greater the potential interference. Sources of changing voltages (e.g all signal lines, clk, AC PWR lines) should change at the minimum rate that allows correct operation. These will always be present to some extent, but need limiting so that they avoid interferring with other equipment & comply with any legislative standards that may be applicable. Emissions can be classified as being broad band (blocks out a complete range of frequencies) or narrowband (blocks out selected frequencies, not others). Examples of broadband sources are unsuppressed motors, relay contacts, car ignitions. The most common examples of narrow band sources are microprocessor clocks. Relays & other EM devices that use make & break contacts generate broad band noise. This can be absorbed by the addition of suppression components, such as capacitors, varistors, directly across the source. The conductors on the circuit that are not grounded will be acting as antennae, radiating RF energy. By keeping these conductors short & running them close to grounded, they become less efficient & will emit less. Power tracks must be wide (making them low impedance at HFs) in this way, they will be less likely to re-radiate interference themselves. If separate power tracks are used on different layers of a pcb, ensure that they are connected together at frequent intervals. Decoupling noise that does get onto the PWR lines by capacitors between PWR & GND is a good idea.

WHAT IS HIGH SPEED DIGITAL BOARD MATERIAL ?

In this tutorial we are going to learn about WHAT IS HIGH SPEED DIGITAL BOARD MATERIAL ?

There are 2 basic types of circuits that fall under the heading of High Frequency-RF/analog (RF or micro- wave) & high-speed digital. Each of these has its own unique requirements, spawning 2 distinct classes of materials. Radio Frequency /analog circuits usually process precision and/or low level signals. As a result, these circuits require much tighter control of parameters pertaining to signal losses. The 2 losses of greatest concern are losses caused by signal reflections, due to impedance mismatch or impedance changes and the loss of signal energy into the dielectric of the material. Some critical applications also must need to focus on losses due to “skin effect.” Impedance variations result from 2 things: material parameters that vary with changes in frequency or temperature, & variations in the processes at the fabricator. The signal lost into the dielectric is a function of the material’s characteristics. Skin effect can be separate controlled through choice of copper type in/on the PCB. Material choice can have a major impact on all these sources of energy loss. Generally, materials of RF/analog domain tightly control parameters such as dielectric thickness, dielectric constant , loss tangent (tan (d) and even copper type. In contrast, digital circuits can tolerate much greater signal loss & still function. Losses are still important in the digital domain, but because of very broad noise margins of digital ICs, lossses usually don’t affect circuit working until they become a very significant portion of the noise budget. This most often occurs at very high operating frequencies. Also, digital circuits are generally very complex & dense & often require very large, high-layer count boards. This tends to put the emphasis for digital materials on process capabilities & cost. These needs have spawned the II group of materials, one geared toward digital applications.

WHAT IS THE FREQUENCY CHARACTERISTICS OF PASSIVE COMPONENTS ?

In this tutorial we are going to learn about WHAT IS THE FREQUENCY CHARACTERISTICS OF PASSIVE COMPONENTS ?

Many designers are ignorant of the frequency limitations of the passive components they use in analog circuit. In Passive components have limited frequency ranges, and operation of the part outside of that range can have some unexpected results. In most cases, a Good passive component will fit on the same pads as a Not good passive component, but not always. Start the design process by carefully considering the High Frequency characteristics of passive components & putting the correct part outline on the board from the start.
Resistors
High Frequency performance of resistance is approximated by the schematic shown in figure:


Resistors are constructed 3 ways, wire wound, carbon composition, & film. It is understand how wire wound resistors can become inductive, because they are coils of Restive wire. Film resistors are also coils of thin metallic film. Therefore, they are also inductive at High Frequencies. The end caps of resistors are parallel, & there will be an associated capacitance. Generally, the resistance will create the parasitic capacitor so “leaky” that the capacitance does not matter. For very high resistances, the capacitance will appear in parallel with the resistance, lowering its impedance at HF’s.
Capacitors
High Frequency performance of capacitors is approximated by the figure

Film & electrolytic capacitors have layers of material wound around each other, which make a parasitic inductance. ceramic capacitors of self inductance effects much smaller, giving them a higher operating frequency. There is also some leakage current from plate to plate R , which appears as a resistance in parallel with the capacitor. The most important parasitic component in a capacitor is the ESR. It is due to resistance within the plates & electrolyte of an electrolytic capacitor. Decoupling capacitor should be low ESR types, as any series resistance limits the effectiveness of the capacitor for ripple & noise rejection. Elevated temperatures severely increases ESR, & can be permanently destructive to capacitors. The leads of Through Hole capacitor also add a parasitic inductance. For small values of capacitance, it is important to keep the lead lengths short. The combination of parasitic inductance & capacitance can produce resonant circuits.

WHAT IS RESISTOR & ITS FORMULA

In this tutorial we are going to learn about WHAT IS RESISTOR & ITS FUNCTION

RESISTOR: Resistance is property of resistor; It opposes the current by doing so it converts electric energy to heat energy

                        R =ρl/a             l – Length

                                                 a – Area

ρ – Resistivity of material in ΩM

Conductor –        Low Resistivity

Semiconductor – Medium Resistivity

Inductor –             High Resistivity

Super Conductor = ρ = 0

Eg.  Mercury at 4.15K temp

Rt = R0 (1+ αt )

R0 = Resistance of material at 0°C

 α  = Temp. Coefficient

t = Change in temp.

WHAT IS OHM’S LAW

  • OHM’S LAW states that at constant temp. Current density is directly proportional to field intensity.
  • At constant temp, potential difference across Element is directly proportional to current flowing through elements 
  •  OHM’S LAW valid only when Conductivity and temp is constant .

INTERVIEW QUESTION FOR PCB DESIGNER

In this tutorial we are going to learn about INTERVIEW QUESTION FOR PCB DESIGNER

  1. What’s thumb rule

In PCB design Thumb rule is 1 Ampere is equal to 1 MM , It means if current flow in trace in 1 MM then trace width should be minimum 1 MM this is called Thumb rule ,Suppose if current flow 10 Ampere then minimum trace width 10 mm but we have to constraint of size then we can manage by increase of copper thinness and remove copper masking on trace where high current is flow.

  • How to decide Trace width

In PCB design trace width depend on signal and

  • What’s EMI & EMC in PCB
  • How to decide layer stack up IN PCB
  • Why use Ground layer
  • How to control EMI EMC in PCB
  • Why use multilayer PCB
  • What is Mixed signal in PCB design
  • What’s is annular ring
  • How to deicide PCB thickness & copper thinness for fabricator

WHAT IS RECTIFIER ?

In this Tutorial we are going to learn about WHAT IS RECTIFIER ?

Rectifier has two applications.

  • Low voltage (electronics application) formed using diode which is part of analog electronics
  • High voltage (electrical application) formed using SCR which is part of Power electronics.

Rectifier is two types

Half wave

Full Wave

Half wave Rectifier

  • Iron core transformer is used.

It is step down transformer which converts a high voltage AC signal into low voltage AC .

Example 220V RMS AC signal can be converted into 44V V RMS AC signal using 5:1 transformer.

The purpose of this step down transformer –

Protects the diode which has low voltage rating ( Max. voltage /breakdown voltage )

For achieving low voltage DC O/P

Diode Performance Rectification

Vi = A pure AC voltage

Operation – Case 1

0 < ∝  < π

  • Vhave +VE cycle
  • So voltage at node ‘a’ is +VE with respective ground .
  • Hence ‘D’ operate in forward Bias (FB) = Short Circuit
  • RL  appears in parallel with secondary winding and hence

                                  Vo = Vi

  • (a small voltage = Forward Voltage drop of 0.7 V will appear across the diode

Case 2

  • π < ∝  < 2π
  • Vi will have –VE cycle
  • Voltage at node ‘a’ becomes –VE with respective ground.
  • Hence ‘D’ will apart in R.B. (Reverse Bias )= Open Circuit

                   Vo = 0

  • The I/P voltage now drop across diode which is acting as open circuit  

Full Wave Rectifier

  • It is also called conventional Full Wave Rectifier .
  • The transformer is Centre tapped.
  • A Centre tapped transformer is used to get two voltage Va & Vb 

As per this both are equal in magnitude but opposite in SIGN  

i.e.  Vb   = – Va

If  Va = Vm sin ∝

Then Vb = – Vm sin ∝

This transformer also converts high voltage AC into Low voltage AC

i.e. It  is step down transformer .

Diode D1 and D2 perform rectification

( convert pure AC into pulsating DC )

Operation – Case 1

0 < ∝  < π

Va is +VE and Vb is –VE so,

 Node ‘a’ is +VE w.r.t. ground

 D1 = Forward Bias = Short Circuit

Node ‘b’ is -VE w.r.t. ground

 D2 = R Bias =Reverse Bias = Open Circuit

RL upper half of secondary winding appear in parallel ,

Therefore Vo= Va

Case 2

π < ∝  < 2π

Va is -VE and Vb is +VE so,

 Node ‘a’ is -VE w.r.t. ground

 D1 = Reverse Bias = Open Circuit

Node ‘b’ is +VE w.r.t. ground

 D2  =Forward Bias = Short Circuit

RL & Lower part of secondary winding appear in parallel ,

Therefore Vo= Vb

WHAT IS PCB DESIGN FLOW ?

In this tutorial we are going to learn about WHAT IS PCB DESIGN FLOW ?

Design Flow Process

Create a set of PCB design flow processes that can used as a guide to step you through the development of a PCB layout. If we follow the best design flow then its helps you avoid duplicating steps. Once you have completed a step, you should never need to repeat it on that design.

1. DESIGN REVIEW

 ̈ The best design review should take place between all applicable disciplines: i.e. hardware Engineer, Project Management, Layout, Mechanical & Manufacturing. For the PCB designer the following information needs to be determined: Layer stack-up & plane layers, PCB thickness & board material, default trace width, component complexity & qty of new components, proto board or production, auto route or manual route, high speed rules, impedance control, test ability and Schedule.

2. COMPONENT DATA SHEETS

Engineering Dept will submit all component data sheets prior to the start date of a PCB layout, of all of the components that can’t be located in your Library Handbook.

3. MECHANICAL DATA SHEET

Engineering Dept will also provide a Board Outline constraint drawing if one is available/ ASAP The mechanical  drawing should be drawn from the top side, include all mounting holes, fixed connector locations, indicate the Layer Stackup & board thickness of the PCB.

4. PART NUMBER & BOARD NAME ASSIGNMENT

After the Engg Dept submits the data sheets, a part no & a board name is assigned to PCB.

5. LIBRARY MANAGEMENT

  As you create library parts, using the naming convention that you developed, populate the applicable blank pages with the new decals, representing the pin assignments & all applicable notes & documentation for each part. Keep the PDF file “Up to Date” every time new parts are built.

6. CUSTOM BOARD OUTLINE

 ̈ Select the correct “Start File” that matches the layering scheme that the Engr has provided & copy the master “Start File” to a new name.

 ̈ Fill out the Title Block.

 ̈ Enter the Board Outline.

 ̈ Add all Mounting/Tooling Holes & Fiducials that are necessary then glue them down.

 ̈ Move the Targets to the outer extremities of the board outline.

 ̈ Fully dimension the board edges & at least one mounting hole.

 ̈ For auto routing should be  Create the “Auto router Keep-in or out” inside the Board Outline.

7. STANDARD BOARD OUTLINE

 ̈ If a Std Board Outline is selected from the Library, the Designer will fill out the Title Block & edit the

text on Layer 26 that will eventually go on the Silkscreen.

 ̈ Setup the correct Layer and Color Scheme.

8. NETLIST

 ̈ At the start of the PCB design, the Engg Dept will provide a net list, from the schematic capture tool.

 ̈ The net list will contain all of the correct Shape Names.

 ̈ The net list will not contain Pin Names over 4 characters long.

 As per given name of PIN should be as per this : Collector = C, Emitter = E, Base = B, Anode = A,

Cathode = K, Source = S, Drain = D, Gate = G, Positive = 1, Negative = 2.

 ̈ Import the net list into Package. If errors are found, in the net list, the Designer will report them to

the Project Engineer. The Project Engineer will fix the problems & provide the Designer with an

updated netlist.

 ̈ After the net list is successfully imported into layout, the Designer will Disperse the parts.

9. REPORTS

 ̈ Create and e-mail to Project Engineer Unused Pins, Part List 2 & Statistic Reports.

 ̈ PCB Designer must review  and make the list for unused components which have two pin.

 ̈ Project Engineer also  must review Unused Pins list of schematic which main project part.

10.PART PLACEMENT

 ̈ The Designer & Engineer will perform the part placement or Engineers suggested layout.

 ̈ The placement must meet the Engrs guidelines & design rules. Engr will provide the DRC.

 ̈ The placement must meet all manufacturing requirements.

 ̈ The placement must meet all routability requirements.

 ̈ Tools/Verify Design – check clearance to ensure no over lapping parts.

11. SPLIT PLANES

 ̈ Use CAM Plane option & use a 2D-Line to separate the different Plane Nets, or use the Split or Mixed Plane option.

 ̈ Use the View or Nets feature to discriminate different nets by color.

12.SILKSCREEN

 ̈ Create Silkscreen (use 0.1mm snap grid) and bottom side etch text.

 ̈ All Ref designators must be moved outside component, & must not exceed 2 different rotations. All Text like company logo and REV must be board inside on TOP side . Default text height/width is .080”/.008” Minimum height/width is .060”/.006”.

13.1ST SET OF QUALITY CONTROL PRINTS

 ̈ 1:1 scale Drill & Assembly drawing laser print/bond paper.

14.FINAL PART PLACEMENT

 ̈ After Split Planes & New library parts are checked, Designer makes final part placement adjustments.

 ̈ PCB Designer will make final silkscreen adjustments.

15.GENERATE OUTPUT FOR MECHANICAL CHECKS USING AutoCAD or PRO-E

TRANSLATORS

16.PREPARE LAYOUT FOR TRACE ROUTING

 ̈ Compare Schematic net list with the PCB Design net list using Netcheck Tools.

17.SETUP DESIGN RULES

 ̈ Setup DRC on “Default Clearance” rules and …

 ̈ Setup DRC on “Net Clearance” rules are to be set up for Voltage, GND & Critical Nets.

 ̈ Set class rules for high speed technology.

18.MANUAL ROUTING

 ̈ Manually Bus route memory sections using Copy or Paste command.

 ̈ Manually fanout all powers that connect to an inner layer plane using Via Share technique.

 ̈ Manually fan out all GND connections so that every GND Pin gets its own Via.

 ̈ Manually route all other Voltages that require large trace widths.

 ̈ Manually route all high-speed matched length traces and critical nets.

 ̈ Use Tools or Verify Design or Check Planes to insure 100% fan out of all SMT Plane Pins.

 ̈ Use Tools or Verify Design or Check Clearances to insure no short circuits.

 ̈ If the design is a 2-Layer board, all voltages should be manually routed/Engineers spec.

19.2nd SET OF QUALITY PRINTS

 ̈ Designer will print all layers that were affected by manual routing & give them to the engineer.

 ̈ If the placement and  pad-stacks have changed run check prints of assembly & drill drawing.

20.SIGNAL INTEGRITY OUTPUT

21.FIX ENGINEERS RED-LINED PRINTS

 ̈ Incorporate all of the Project Engineers corrections.

 ̈ If there were many traces, PCB Designer will create a new set of check prints.

22.TESTABILITY

 Below are the following questions:

 ̈ Does every Net need a test point/just some of the nets?

 ̈ Do voltage nets require extra test points?

 ̈ Do non-connected pins need to be testable?

̈ Can vias be used as test points, or do they have to be “Bottom Side” non-drilled Pads?

 ̈ What size do the test points have to be, what is the point to point spacing requirements & amount of pins per square inch?

If PCB Design requires testability on every net, the Designer will add a test point for every net, using

DFT program & place the test points, near the pins, of the net it belongs to.

23.ROUTE REMAINDER OF NON-CRITICAL ROUTES

 ̈ If the PC Board has a large number of production boards made, it must be 100 % manually which can minimize the trace length & layer.

 ̈ If Engineer requested a quick turn prototype, use an autorouter to route remainder of pcb.

 ̈ If autorouting used, clean up the traces on all layers after the router has completed 100%

 ̈ Make and save a pre-auto routed version of the PCB. This will be use for future revisions.

24.FINAL DRC CHECKS

 ̈ PCB Designer & Project Engr: Tools/Verify Design – Check Clearances, Continuity & Panes.

25.3rd SET OF QUALITY PRINTS

 ̈ Make the  check prints of all Routed Layers, Silk-screens, Solder & Paste Masks.

 ̈ Make the check prints of final AutoCAD Drill & Assembly Drawings.

 ̈ Make final CAE Netlist with final CAD Netlist.

26.FINAL CAM OUTPUT

 ̈Generate final prints of  AutoCAD Assembly & Drill Drawings.

 ̈ Create  Gerber Data, Drill Data & Fabrication Drawing for Febrication.

 ̈ Import the Geber file into CAM350 to extract an IPC-D-356 Netlist.

 ̈ Create Assembly X/Y Coordinate Data.

WHAT IS MULTI LAYER PCB ?

In this tutorial we are going to learn about WHAT IS MULTI LAYER PCB

Why we need Multi layer : A multi layer PCB board is depend on schematic complexity , the situations where the design connection is not handled by two layer and second reason if special requirement of impedance control or other function .

  • How to make Multilayer PCB : A Pre-preg material of thin layer  between each layer of PCB , thus making a sandwich assembly
  •  Multilayer Routing: In Multilayer PCB have two reference Planes and a signal via , The signal via allows a signal to flow through all the planes. A common  via is connected to one of the planes next to the signal via and serves to reduce the area through which the signal passes through. If use this technique to reduce noise and cross talk.
  • Multilayer PCB layer: multilayer PCBs could be 4 layer to 50 layer its depend on schematic complexity.
  • Multilayer PCB Advantage:  multilayer PCBs  advantage have  high reliability and small size of PCB
  • Multilayer PCB Disadvantage:  Multilayer PCB of  the initial costs are higher than that of one-layered PCBs. Also, repairing a multilayer PCB is quite difficult.

Multilayer PCB applications

  • If the complexity of interconnection in sub-systems requires complicated and expensive Wiring or harnessing.
  • If the  frequency requirements call for careful control and uniformity of conductor wave
  • Impedance with minimum distortions and signal propagation, and where the uniformity of these characteristics from board-to-board is important
  •  When coupling or shielding of a large number of connections is necessary
  • With multi layers, all interconnections can be placed on internal layers, and a heat sink of wide solid copper can be placed on the outer surfaces.