In this tutorial we are going to learn about What is Power Planes and Power Distribution In PCB Design?
Which Supply to Use and Supply Decoupling
PWR leads coming onto the board should be decoupled to GND at the point where they enter the board.
That way, all return currents from the decoupling components return directly to the PWR supply without passing through the GND planes of the board. While inductive decoupling components or resistive decoupling components can be effective, the best designs route ±18V to ±24V to each board & use small regulators, along with decoupling, to derive ±12V to ±15V for the board/individual devices. the single supply AC devices: route +8V – +15V to the individual boards, with separate +5V regulators & decoupling on each board. One of the advantages of using devices in designs is the fact that they only require a single +5V supply, without the need to decouple positive &d negative supplies. A/D converters & D/A converters, in particular, need regulators & decoupling close to them to reduce the possibility of noise coupling from the rest of the circuitry. Most A/D converters also have a low-current digital section that needs to be connected to the quiet analog supply & GND, usually through some decoupling. Having pins marked Digital Ground on an A/D converter usually means that they are the IC’s digital GND, not that they should be connected to the system’s DGND. Most A/Ds also specify that even their high-current digital sections should be connected to an analog supply & GND, using higher-power decoupling, to obtain best performance. In general, noisy digital supplies & GND need to be kept away from high-performance A/D converters, except in the area where the digital outputs are developed. In order to have analog PWR & GNDs on their supplies but DGND plane underneath their digital outputs, most A/D converters should straddle the split between the GNDs in some fashion.
All analog circuitry needs decoupling on its PWR leads to shunt both HF & LF noise to GND. Its generally recommended that designers use either a 0.1 μF or 0.01 μF capacitor to decouple the PWR pins of each analog IC to ground. At various distances, place larger value capacitors, usually 10 μF – 47 μF, in parallel with 0.1 μF/0.01 μF units. In particular, high performance ICs must have each supply decoupled to Ground. The smaller value capacitor should be placed as close to the IC as possible, the leads on these caps must be kept very short. The best technique is to have the PWR feed from the PWR plane through a via to the capacitor & IC pins, with the capacitor between the via & the IC. The GND connection is particularly important, & should be made with 3 – 4 vias connecting to the capacitor & thus to the IC pins. The inductances of vias are then effectively in parallel. For examples of this technique. SM capacitors are best b’cos their connection pads have almost no lead inductance. In addition, SM electrolytic capacitors can be used for the 10 μF – 47 μF units. Both aluminum & tantalum capacitors are available in these values, with tantalum having the lower ESR but also being more prone to power supply transients or reversal.